1. Field of the Invention
This invention relates to an improvement applicable to a power on reset circuit employable for an integrated circuit. More specifically, this invention relates to an improvement developed for simplifying the circuit structure of a power on reset circuit which issues a one shot pulse without fail, even if the increase rate of the power supply voltage is less and for decreasing the power consumption required thereby.
2. Prior Art Statement
A power on reset circuit is defined as a circuit which issues a one shot pulse, for the purpose to cause every electronic component composing a circuit to return to the initial positions, in response to a signal indicating that a power supply is turned on for the circuit.
The power on reset circuit available in the prior art consists of a charging capacitor and a circuit for charging the capacitor, which circuit for charging the capacitor is composed of a resistor or a constant current power supply, and has a function to issue a one shot pulse, in response to a signal indicating that the power supply is turned on. In such a power on reset circuit as is described above, there are some chances in which the period required for a power supply voltage to reach the rated voltage is longer than the period required for a capacitor to be charged until the rated voltage. In such a case, a one shot pulse or a power on reset signal is not issued.
This problem can be solved by technology disclosed in JP-A 63-246919, JP-A 4-72912 and/or JP-A 6-196989.
The power on reset circuit disclosed in JP-A 63-246919 or the power on reset circuit illustrated in FIG. 1 attached to this application, is provided with a flip-flop circuit which is set simultaneously with application of an electronic power supply, and a circuit for sending a power supply voltage which sets the flip-flop circuit a predetermined period later than the time at which the power supply voltage has arrived at a predetermined value of voltage.
More specifically, the power on reset circuit shown in JP-A 63-246919 illustrated in FIG. 1 attached to this specification has a flip-flop circuit (2) consisting of two inverters (2a) and (2b) to sense and hold an increase of the power supply voltage, a capacitor (3) connected the flip-flop circuit (2), a MOS transistor (4) and a power supply voltage sensing circuit (10). The power supply voltage sensing circuit (10) has a MOS diode array (14) consisting of a 2-stage inverter (11) and (12) connected the output terminal of the flip-flop circuit (2) and plural MOS diodes (13), a capacitor (15) and a MOS transistor (16).
Since the power on reset circuit shown in JP-A 63-246919 is a quite ordinary power on reset circuit having a capacitor, resistors and inverters, further comprising a supporting circuit to be connected to the quite ordinary power on reset circuit in parallel for the purpose to cause the supporting circuit to compulsively issue a signal for resetting the flip-flop circuit (2), the structure of the power on reset circuit shown in JP-A 63-246919 (10) is fairly complicated.
The power on reset circuit disclosed in JP-A 4-72912 or the power on reset circuit illustrated in FIG. 2 attached to this application, is provided with a power supply voltage sensing circuit (20) which senses whether or not the power supply voltage has reached up to a predetermined voltage, a delay circuit (30) which delays the output signal of the power supply voltage sensing circuit (20), and a wave form reverting circuit (40).
More specifically, the power supply voltage sensing circuit (20) has a series circuit of a resistor (21) and a parallel circuit of an n channel MOS diode (22) and a series circuit of a resistor (23) and a resistor (24), the series circuit being inserted between the power supply Vcc and the ground potential. The connection node at which the resistor (21) and the parallel circuit is connected, is called N.sub.1. At the connection node N.sub.2, the resistors (23) and (24) are inverter (25) designated to operate with the power supply voltage and the source of an n channel MOS FET (26). The inverter (25) is composed of a p channel MOS FET (25a) and an n channel MOS FET (25b). The gate of the n channel MOS FET (26) is connected to the output terminal of the inverter (25), and the drain of the n channel MOS FET (26) is connected the ground level.
The delay circuit (30) is composed of an n channel MOS FET (31) of which the source is connected to the inverter (25) and of which the gate is connected the power supply potential Vcc and a capacitor (32) connected between the drain of the n channel MOS FET (31) and the ground potential. The wave form reverting circuit (40) is composed of an inverter (41) of which the input terminal is connected to a connection node (N.sub.3) connecting the n channel MOS FET (31) and the capacitor (32), and a p channel MOS FET (42) which is connected between the power supply potential (Vcc) and the node (N.sub.3) and of which the gate is connected to the output terminal of the inverter (41).
Thus, since the power on reset circuit disclosed in JP-A 4-72912 is based on the idea that the voltage applied between the Vcc terminal and the ground terminal is divided by resistors (21), (23) and (24), the electric current continues flowing through the resistors (21), (23) and (24) even after the one shot pulse is issued. This means the power on reset circuit disclosed in JP-A 4-72912 is accompanied by a drawback in which electric power consumption is not necessarily marginal.
The power on reset circuit disclosed in JP-A 6-196989 or the power on reset circuit illustrated in FIG. 3 attached to this application, is provided with a series circuit composed of a p channel normally off FET (51) and a voltage control means (52), connected between the Vdd and the ground potential. The voltage control means (52) is composed of an n channel normally on FET (52a) of which the source is connected to the drain of the p channel normally off FET (51) and an n channel normally of FET (52b) of which the gate and the drain are connected to the gate and the source of the n channel normally on FET (52a). The source of the n channel normally off FET (52b) is grounded.
The drain of an n channel normally off FET (54) and a pulse generator means (53) are connected to the output terminal of the voltage control circuit (52). The source of the n channel normally off FET (54) is grounded. The pulse generator means (53) is composed of a p channel normally off FET (53a) of which the source is connected to Vdd, a capacitor (53b) which is connected between the drain of the p channel normally off FET (53a) and the ground potential and an inverter (53c) connected the connection point of the drain of the p channel normally off FET (53a) and the capacitor (53b).
The output terminal of the inverter (53c) is the output terminal of the power on reset circuit disclosed in JP-A 6-196989, and is connected an inverter (55) of which the output terminal is connected the gates of the p channel normally off FET (51) and of the n channel normally off FET (54).
In the power on reset circuit disclosed in JP-A 6-196989, the inverter (55) is essential for the purpose to make the power consumption zero, after the pulse generator means (53) issued a one shot pulse.
The foregoing prior art statement has clarified that any of the power on reset circuits which issue a one shot pulse without fail, even if the increase rate of the power supply voltage is less, available in the prior art, can not fully satisfy the requirements imposed thereon, particularly in the viewpoints of the circuit structure, power consumption or the like.